The present invention relates to a semiconductor device having multi-level wiring and a method of manufacturing multi-level wiring for a semiconductor device.
In recent years, the integration density of semiconductor devices has been raised and the multi-level wiring have been used more frequently, as the scale of the systems realized by the use of semiconductor devices is increased and the fabrication technology for semiconductor devices with fine geometry is advanced. The method which is general for the formation of multi-level wiring in the conventional semiconductor devices is as described below. First, an insulating layer is formed on a semiconductor substrate comprising the required semiconductor elements. A contact hole is formed at a required position in the insulating layer, and then, a first level of wiring is formed. Subsequently, the following steps (1) to (3) are repeated for a necessary number of times: (1) forming an intermediate insulating film, (2) creating a through hole at a required position, and (3) forming wiring for second and subsequent levels.
With the increase in the integration density of semiconductor devices, the space between the wiring also decreases. Because of this, the parasitic capacitance incidental to the wiring increases. A multi-level wiring formed according to the above method has a structure in which an intermediate insulating film is filled between the adjacent wiring without exception. For this reason, the parasitic capacitance incidental to the wiring is further increased.
A discussion about the parasitic capacitance between the wiring is reported, for example, by R. L. M. DANG et al. entitled "Coupling Capacitances for Two-Dimensional Wires"[in IEEE Electron Device Letters, Vol. EDL-2, No. 8, pp. 196 to 197, August 1981. Although this report does not discuss the structure of a multi-level wiring per se, it shows that the parasitic capacitance between the wiring of the same level increases relatively when the line width and spacing of the wiring is decreased. Further, an analysis of the capacitance of a three-level wiring according to a three-dimensional simulation is reported by Y. Ushiku et al. entitled "A THREE-LEVEL WIRING CAPACITANCE ANALYSIS FOR VLSIs USING A THREE-DIMENSIONAL SIMULATOR" in IEDM 88, PP. 340 to 343. This report shows the changes in the coupling capacitance due to the film thickness of the wiring, the pitch of the wiring, the film thickness of the intermediate insulating film and the like, and the change in the coupling capacitance due to the scaling. What is described in these reports is useful for minimizing the parasitic capacitance between the wiring in the conventional structures in which an intermediate insulating film is filled between the adjacent wirings.
Demands for fast operation of the semiconductor devices are recently increasing as the integration density of the semiconductor devices increases. As is clear also from this trend, a reduction in the parasitic capacitance between the wiring is a very important task.